[Nets-seminars] REMINDER: talk by Phil Watts, UCL EE, 2 PM (imminently)

Brad Karp B.Karp at cs.ucl.ac.uk
Tue Mar 4 13:53:50 GMT 2014


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Just a quick reminder about this talk by Phil Watts of UCL EE.

Please join us!

- -Brad, bkarp at cs.ucl.ac.uk

- -------- Original Message --------
Subject: talk by Phil Watts, UCL EE, 2 PM Tuesday 4 Mar
Date: Mon, 03 Mar 2014 18:29:06 +0000
From: Brad Karp <B.Karp at cs.ucl.ac.uk>
To: nets <nets at cs.ucl.ac.uk>, nets-seminars at cs.ucl.ac.uk
CC: Brad Karp <B.Karp at cs.ucl.ac.uk>

Greetings, everyone.

Phil Watts, previously a postdoc in EE at Cambridge, who then joined
UCL EE as a Lecturer in 2011, does interesting work at the junction
between optical networking and computer systems. Specifically, he
works on how to use optical networking to build lower-latency,
lower-energy top-of-rack switches for data centers, and how to build a
low-latency, low-power shared memory system for multi-core and
multi-socket servers.

He'll be coming over to give a talk in our usual Tuesday afternoon
group meeting slot, at 2 PM tomorrow, the 4th of March.

Phil is very interested in finding ways to collaborate with systems
and networking researchers like us (which should be very natural,
given the topics he's working on).

Title, abstract, and bio follow.

- -Brad, bkarp at cs.ucl.ac.uk

- ---

Speaker: Phil Watts, UCL EE

Time and place: 2 PM, Tuesday 4th March, MPEB 6.12

Title: Toward Zero-Latency Photonic Switching

Abstract:

Developments in silicon photonics could see photonic network elements
co-packaged with processors creating low energy networks-on-chip (NoC)
or direct links between processors across a data centre.   However,
although it is easy to show that basic photonic network elements have
lower latency and energy requirements than their electronic
counterparts, on the system level the issue is not so clear cut.  For
example, the scheduling overhead incurred in reconfiguring photonic
switches can be a significant overhead for the short messages created
by shared memory networks and Ethernet.  Furthermore, recent NoC
results have suggested that the edge buffering required in photonic
networks results in greater overall energy consumption than electronic
NoCs.  Due to the fundamental differences between electronic and
photonic networks, new architectures and scheduling algorithms are
required to exploit photonics in future systems.  This talk will
describe low energy, low latency network architectures for two
scenarios: (1) an optical top-of-rack switch for data centres and (2)
a shared memory coherence network for cache coherent multicore chips
or multi-socket servers.

Bio:

Dr Philip Watts was awarded the PhD from UCL in 2008 for research in
digital signal processing (DSP) for optical fibre communications.
- From 2008 to 2011 he was a Research Fellow at the Computer Laboratory,
University of Cambridge where he developed his current research in
photonic interconnects for high performance computer systems.  He was
awarded an EPSRC Research Fellowship in 2010 and moved to his current
position of Lecturer in the Electronic and Electrical Engineering
Department at UCL in 2011.  He has published more than 50 conference
and journal papers and two patents in the fields of DSP for optical
communications and optical interconnect systems including 14 invited
papers.  During his academic research career he has collaborated or
consulted with Intel, Extera, Ericson, Huawei, Xilinx and Inphi as
well as gaining 10 years industrial optical product development
experience with BAE Systems and Nortel prior to his PhD.  He was
awarded the IEEE Photonics Society postgraduate student fellowship in
2006, the Royal Commission for the Exhibition of 1851 Brunel Research
Fellowship in 2008 and is a co-investigator on the EPSRC UNLOC
programme grant.  He serves on the technical programme committees of
Field Programmable Logic (FPL) and the IEEE Symposium on High
Performance Interconnects.
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