[Nets-seminars] UCL EE seminar 6th June 2014 16:00 GS/102

[Richard G. Clegg]

Our next seminar (and the last of this season) is this Friday, 6th June 
2014 at 16:00.  It will be in GS/102.  I look forward to seeing you all 
there.

Towards Zero Latency Photonic Switching

Developments in silicon photonics could see photonic network elements co-packaged with processors creating low energy networks-on-chip (NoC) or direct links between processors across a data centre.   However, although it is easy to show that basic photonic network elements have lower latency and energy requirements than their electronic counterparts, on the system level the issue is not so clear cut.  For example, the scheduling overhead incurred in reconfiguring photonic switches can be a significant overhead for the short messages created by shared memory networks and Ethernet.  Furthermore, recent NoC results have suggested that the edge buffering required in photonic networks results in greater overall energy consumption than electronic NoCs.  Due to the fundamental differences between electronic and photonic networks, new architectures and scheduling algorithms are required to exploit photonics in future systems.  This talk will describe low energy, low latency network architectures for two scenarios: (1) a shared memory coherence network for cache coherent multicore chips or multi-socket servers; (2) an optical top-of-rack switch for data centres

Bio

Dr Philip Watts was awarded the PhD from UCL in 2008 for research in digital signal processing (DSP) for optical fibre communications.  From 2008 to 2011 he was a Research Fellow at the Computer Laboratory, University of Cambridge where he developed his current research in photonic interconnects for high performance computer systems.  He was awarded an EPSRC Research Fellowship in 2010 and moved to his current position of Lecturer in the Electronic and Electrical Engineering Department at UCL in 2011.  He has published more than 50 conference and journal papers and two patents in the fields of DSP for optical communications and optical interconnect systems including 14 invited papers.  During his academic research career he has collaborated or consulted with Intel, Extera, Ericson, Huawei, Xilinx and Inphi as well as gaining 10 years industrial optical product development experience with BAE Systems and Nortel prior to his PhD.  He was awarded the IEEE Photonics Society postgraduate student fellowship in 2006, the Royal Commission for the Exhibition of 1851 Brunel Research Fellowship in 2008 and is a co-investigator on the EPSRC UNLOC programme grant.  He serves on the technical programme committees of Field Programmable Logic (FPL) and the IEEE Symposium on High Performance Interconnects.

-- 
Richard G. Clegg,
Dept of Elec. Eng.,
University College London
http://www.richardclegg.org/