[Sumover-dev] [svn commit] r3938 - in vic/branches/mpeg4: cpu linux
render
sumover-dev at cs.ucl.ac.uk
sumover-dev at cs.ucl.ac.uk
Thu Nov 16 10:27:12 GMT 2006
Author: barz
Date: Thu Nov 16 10:26:25 2006
New Revision: 3938
Added:
vic/branches/mpeg4/cpu/
vic/branches/mpeg4/cpu/cpudetect.c (contents, props changed)
vic/branches/mpeg4/cpu/cpudetect.h (contents, props changed)
vic/branches/mpeg4/cpu/cpuid.asm (contents, props changed)
vic/branches/mpeg4/cpu/cpuid.cpp (contents, props changed)
vic/branches/mpeg4/cpu/cputable.h (contents, props changed)
Removed:
vic/branches/mpeg4/linux/
Modified:
vic/branches/mpeg4/config_arch.h
vic/branches/mpeg4/configure.in
vic/branches/mpeg4/main.cpp
vic/branches/mpeg4/render/color-swscale.cpp
vic/branches/mpeg4/vic.vcproj
Log:
add runtime cpu detection in win32, win64, and powerpc
Modified: vic/branches/mpeg4/config_arch.h
==============================================================================
--- vic/branches/mpeg4/config_arch.h (original)
+++ vic/branches/mpeg4/config_arch.h Thu Nov 16 10:26:25 2006
@@ -8,12 +8,10 @@
#define ARCH_X86 1
/* Runtime CPU detection */
-#define HAVE_MMX
-#define HAVE_MMX2
+#define RUNTIME_CPUDETECT
/* Only use during compliation */
#if defined(RUNTIME_CPUDETECT)
-#undef HAVE_MMX
#define HAVE_MMX
#define HAVE_MMX2
#define HAVE_SSE
Modified: vic/branches/mpeg4/configure.in
==============================================================================
--- vic/branches/mpeg4/configure.in (original)
+++ vic/branches/mpeg4/configure.in Thu Nov 16 10:26:25 2006
@@ -198,13 +198,11 @@
V_CPUDETECT=""
AC_ARG_ENABLE(cpudetect, --disable-cpudetect Enable or disable runtime cpu detection, cpudetect="no", cpudetect="yes")
-if test "$arch" = "x86_32" -o "$arch" = "x86_64"; then
- if test "$cpudetect" = "yes"; then
+if test "$cpudetect" = "yes"; then
echo "using CPU runtime detection..."
- V_OBJ="$V_OBJ linux/cpudetect.o"
+ V_OBJ="$V_OBJ cpu/cpudetect.o"
V_CPUDETECT="-DRUNTIME_CPUDETECT"
- fi
-fi
+i
V_H261AS=""
Added: vic/branches/mpeg4/cpu/cpudetect.c
==============================================================================
--- (empty file)
+++ vic/branches/mpeg4/cpu/cpudetect.c Thu Nov 16 10:26:25 2006
@@ -0,0 +1,623 @@
+#include "cpudetect.h"
+
+CpuCaps gCpuCaps;
+
+#ifdef HAVE_MALLOC_H
+#include <malloc.h>
+#endif
+#include <stdlib.h>
+
+#if defined(ARCH_X86) || defined(ARCH_X86_64)
+
+#include <stdio.h>
+#include <string.h>
+
+#if defined (__NetBSD__) || defined(__OpenBSD__)
+#include <sys/param.h>
+#include <sys/sysctl.h>
+#include <machine/cpu.h>
+#endif
+
+#if defined(__FreeBSD__) || defined(__DragonFly__)
+#include <sys/types.h>
+#include <sys/sysctl.h>
+#endif
+
+#ifdef __linux__
+#include <signal.h>
+#endif
+
+#ifdef WIN32
+#include <windows.h>
+#endif
+
+#ifdef __AMIGAOS4__
+#include <proto/exec.h>
+#endif
+
+//#define X86_FXSR_MAGIC
+/* Thanks to the FreeBSD project for some of this cpuid code, and
+ * help understanding how to use it. Thanks to the Mesa
+ * team for SSE support detection and more cpu detect code.
+ */
+
+/* I believe this code works. However, it has only been used on a PII and PIII */
+
+static void check_os_katmai_support( void );
+
+#if 1
+// return TRUE if cpuid supported
+static int has_cpuid(void)
+{
+ long a, c;
+
+// code from libavcodec:
+ __asm__ __volatile__ (
+ /* See if CPUID instruction is supported ... */
+ /* ... Get copies of EFLAGS into eax and ecx */
+ "pushf\n\t"
+ "pop %0\n\t"
+ "mov %0, %1\n\t"
+
+ /* ... Toggle the ID bit in one copy and store */
+ /* to the EFLAGS reg */
+ "xor $0x200000, %0\n\t"
+ "push %0\n\t"
+ "popf\n\t"
+
+ /* ... Get the (hopefully modified) EFLAGS */
+ "pushf\n\t"
+ "pop %0\n\t"
+ : "=a" (a), "=c" (c)
+ :
+ : "cc"
+ );
+
+ return (a!=c);
+}
+#endif
+
+static void
+do_cpuid(unsigned int ax, unsigned int *p)
+{
+#if 0
+ __asm __volatile(
+ "cpuid;"
+ : "=a" (p[0]), "=b" (p[1]), "=c" (p[2]), "=d" (p[3])
+ : "0" (ax)
+ );
+#else
+// code from libavcodec:
+ __asm __volatile
+ ("mov %%"REG_b", %%"REG_S"\n\t"
+ "cpuid\n\t"
+ "xchg %%"REG_b", %%"REG_S
+ : "=a" (p[0]), "=S" (p[1]),
+ "=c" (p[2]), "=d" (p[3])
+ : "0" (ax));
+#endif
+
+}
+
+void GetCpuCaps( CpuCaps *caps)
+{
+ unsigned int regs[4];
+ unsigned int regs2[4];
+
+ memset(caps, 0, sizeof(*caps));
+ caps->isX86=1;
+ caps->cl_size=32; /* default */
+ if (!has_cpuid()) {
+ // mp_msg(MSGT_CPUDETECT,MSGL_WARN,"CPUID not supported!??? (maybe an old 486?)\n");
+ return;
+ }
+ do_cpuid(0x00000000, regs); // get _max_ cpuid level and vendor name
+ // mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU vendor name: %.4s%.4s%.4s max cpuid level: %d\n",
+ // (char*) (regs+1),(char*) (regs+3),(char*) (regs+2), regs[0]);
+ if (regs[0]>=0x00000001)
+ {
+ char *tmpstr, *ptmpstr;
+ unsigned cl_size;
+
+ do_cpuid(0x00000001, regs2);
+
+ caps->cpuType=(regs2[0] >> 8)&0xf;
+ caps->cpuModel=(regs2[0] >> 4)&0xf;
+
+// see AMD64 Architecture Programmer's Manual, Volume 3: General-purpose and
+// System Instructions, Table 3-2: Effective family computation, page 120.
+ if(caps->cpuType==0xf){
+ // use extended family (P4, IA64, K8)
+ caps->cpuType=0xf+((regs2[0]>>20)&255);
+ }
+ if(caps->cpuType==0xf || caps->cpuType==6)
+ caps->cpuModel |= ((regs2[0]>>16)&0xf) << 4;
+
+ caps->cpuStepping=regs2[0] & 0xf;
+
+ // general feature flags:
+ caps->hasTSC = (regs2[3] & (1 << 8 )) >> 8; // 0x0000010
+ caps->hasMMX = (regs2[3] & (1 << 23 )) >> 23; // 0x0800000
+ caps->hasSSE = (regs2[3] & (1 << 25 )) >> 25; // 0x2000000
+ caps->hasSSE2 = (regs2[3] & (1 << 26 )) >> 26; // 0x4000000
+ caps->hasMMX2 = caps->hasSSE; // SSE cpus supports mmxext too
+ cl_size = ((regs2[1] >> 8) & 0xFF)*8;
+ if(cl_size) caps->cl_size = cl_size;
+
+ ptmpstr=tmpstr=GetCpuFriendlyName(regs, regs2);
+ while(*ptmpstr == ' ') // strip leading spaces
+ ptmpstr++;
+
+ strcpy(caps->cpuname, ptmpstr);
+ // mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: %s ", ptmpstr);
+ free(tmpstr);
+ // mp_msg(MSGT_CPUDETECT,MSGL_INFO,"(Family: %d, Model: %d, Stepping: %d)\n",
+ // caps->cpuType, caps->cpuModel, caps->cpuStepping);
+
+ }
+ do_cpuid(0x80000000, regs);
+ if (regs[0]>=0x80000001) {
+ // mp_msg(MSGT_CPUDETECT,MSGL_V,"extended cpuid-level: %d\n",regs[0]&0x7FFFFFFF);
+ do_cpuid(0x80000001, regs2);
+ caps->hasMMX |= (regs2[3] & (1 << 23 )) >> 23; // 0x0800000
+ caps->hasMMX2 |= (regs2[3] & (1 << 22 )) >> 22; // 0x400000
+ caps->has3DNow = (regs2[3] & (1 << 31 )) >> 31; //0x80000000
+ caps->has3DNowExt = (regs2[3] & (1 << 30 )) >> 30;
+ }
+ if(regs[0]>=0x80000006)
+ {
+ do_cpuid(0x80000006, regs2);
+ // mp_msg(MSGT_CPUDETECT,MSGL_V,"extended cache-info: %d\n",regs2[2]&0x7FFFFFFF);
+ caps->cl_size = regs2[2] & 0xFF;
+ }
+ // mp_msg(MSGT_CPUDETECT,MSGL_V,"Detected cache-line size is %u bytes\n",caps->cl_size);
+#if 0
+ // mp_msg(MSGT_CPUDETECT,MSGL_INFO,"cpudetect: MMX=%d MMX2=%d SSE=%d SSE2=%d 3DNow=%d 3DNowExt=%d\n",
+ gCpuCaps.hasMMX,
+ gCpuCaps.hasMMX2,
+ gCpuCaps.hasSSE,
+ gCpuCaps.hasSSE2,
+ gCpuCaps.has3DNow,
+ gCpuCaps.has3DNowExt );
+#endif
+
+ /* FIXME: Does SSE2 need more OS support, too? */
+#if defined(__linux__) || defined(__FreeBSD__) || defined(__NetBSD__) || defined(__CYGWIN__) || defined(__OpenBSD__) || defined(__DragonFly__) || defined(__APPLE__)
+ if (caps->hasSSE)
+ check_os_katmai_support();
+ if (!caps->hasSSE)
+ caps->hasSSE2 = 0;
+#else
+ caps->hasSSE=0;
+ caps->hasSSE2 = 0;
+#endif
+// caps->has3DNow=1;
+// caps->hasMMX2 = 0;
+// caps->hasMMX = 0;
+
+#ifndef HAVE_MMX
+ if(caps->hasMMX) // mp_msg(MSGT_CPUDETECT,MSGL_WARN,"MMX supported but disabled\n");
+ caps->hasMMX=0;
+#endif
+#ifndef HAVE_MMX2
+ if(caps->hasMMX2) // mp_msg(MSGT_CPUDETECT,MSGL_WARN,"MMX2 supported but disabled\n");
+ caps->hasMMX2=0;
+#endif
+#ifndef HAVE_SSE
+ if(caps->hasSSE) // mp_msg(MSGT_CPUDETECT,MSGL_WARN,"SSE supported but disabled\n");
+ caps->hasSSE=0;
+#endif
+#ifndef HAVE_SSE2
+ if(caps->hasSSE2) // mp_msg(MSGT_CPUDETECT,MSGL_WARN,"SSE2 supported but disabled\n");
+ caps->hasSSE2=0;
+#endif
+#ifndef HAVE_3DNOW
+ if(caps->has3DNow) // mp_msg(MSGT_CPUDETECT,MSGL_WARN,"3DNow supported but disabled\n");
+ caps->has3DNow=0;
+#endif
+#ifndef HAVE_3DNOWEX
+ if(caps->has3DNowExt) // mp_msg(MSGT_CPUDETECT,MSGL_WARN,"3DNowExt supported but disabled\n");
+ caps->has3DNowExt=0;
+#endif
+}
+
+
+#define CPUID_EXTFAMILY ((regs2[0] >> 20)&0xFF) /* 27..20 */
+#define CPUID_EXTMODEL ((regs2[0] >> 16)&0x0F) /* 19..16 */
+#define CPUID_TYPE ((regs2[0] >> 12)&0x04) /* 13..12 */
+#define CPUID_FAMILY ((regs2[0] >> 8)&0x0F) /* 11..08 */
+#define CPUID_MODEL ((regs2[0] >> 4)&0x0F) /* 07..04 */
+#define CPUID_STEPPING ((regs2[0] >> 0)&0x0F) /* 03..00 */
+
+char *GetCpuFriendlyName(unsigned int regs[], unsigned int regs2[]){
+#include "cputable.h" /* get cpuname and cpuvendors */
+ char vendor[13];
+ char *retname;
+ int i;
+
+ if (NULL==(retname=malloc(256))) {
+ // mp_msg(MSGT_CPUDETECT,MSGL_FATAL,"Error: GetCpuFriendlyName() not enough memory\n");
+ exit(1);
+ }
+
+ sprintf(vendor,"%.4s%.4s%.4s",(char*)(regs+1),(char*)(regs+3),(char*)(regs+2));
+
+ do_cpuid(0x80000000,regs);
+ if (regs[0] >= 0x80000004)
+ {
+ // CPU has built-in namestring
+ retname[0] = '\0';
+ for (i = 0x80000002; i <= 0x80000004; i++)
+ {
+ do_cpuid(i, regs);
+ strncat(retname, (char*)regs, 16);
+ }
+ return retname;
+ }
+
+ for(i=0; i<MAX_VENDORS; i++){
+ if(!strcmp(cpuvendors[i].string,vendor)){
+ if(cpuname[i][CPUID_FAMILY][CPUID_MODEL]){
+ snprintf(retname,255,"%s %s",cpuvendors[i].name,cpuname[i][CPUID_FAMILY][CPUID_MODEL]);
+ } else {
+ snprintf(retname,255,"unknown %s %d. Generation CPU",cpuvendors[i].name,CPUID_FAMILY);
+ // mp_msg(MSGT_CPUDETECT,MSGL_WARN,"unknown %s CPU:\n",cpuvendors[i].name);
+ // mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Vendor: %s\n",cpuvendors[i].string);
+ // mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Type: %d\n",CPUID_TYPE);
+ // mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Family: %d (ext: %d)\n",CPUID_FAMILY,CPUID_EXTFAMILY);
+ // mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Model: %d (ext: %d)\n",CPUID_MODEL,CPUID_EXTMODEL);
+ // mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Stepping: %d\n",CPUID_STEPPING);
+ // mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Please send the above info along with the exact CPU name"
+ // "to the MPlayer-Developers, so we can add it to the list!\n");
+ }
+ }
+ }
+ retname[255] = 0;
+
+ //printf("Detected CPU: %s\n", retname);
+ return retname;
+}
+
+#undef CPUID_EXTFAMILY
+#undef CPUID_EXTMODEL
+#undef CPUID_TYPE
+#undef CPUID_FAMILY
+#undef CPUID_MODEL
+#undef CPUID_STEPPING
+
+
+#if defined(__linux__) && defined(_POSIX_SOURCE) && defined(X86_FXSR_MAGIC)
+static void sigill_handler_sse( int signal, struct sigcontext sc )
+{
+ // mp_msg(MSGT_CPUDETECT,MSGL_V, "SIGILL, " );
+
+ /* Both the "xorps %%xmm0,%%xmm0" and "divps %xmm0,%%xmm1"
+ * instructions are 3 bytes long. We must increment the instruction
+ * pointer manually to avoid repeated execution of the offending
+ * instruction.
+ *
+ * If the SIGILL is caused by a divide-by-zero when unmasked
+ * exceptions aren't supported, the SIMD FPU status and control
+ * word will be restored at the end of the test, so we don't need
+ * to worry about doing it here. Besides, we may not be able to...
+ */
+ sc.eip += 3;
+
+ gCpuCaps.hasSSE=0;
+}
+
+static void sigfpe_handler_sse( int signal, struct sigcontext sc )
+{
+ // mp_msg(MSGT_CPUDETECT,MSGL_V, "SIGFPE, " );
+
+ if ( sc.fpstate->magic != 0xffff ) {
+ /* Our signal context has the extended FPU state, so reset the
+ * divide-by-zero exception mask and clear the divide-by-zero
+ * exception bit.
+ */
+ sc.fpstate->mxcsr |= 0x00000200;
+ sc.fpstate->mxcsr &= 0xfffffffb;
+ } else {
+ /* If we ever get here, we're completely hosed.
+ */
+ // mp_msg(MSGT_CPUDETECT,MSGL_V, "\n\n" );
+ // mp_msg(MSGT_CPUDETECT,MSGL_V, "SSE enabling test failed badly!" );
+ }
+}
+#endif /* __linux__ && _POSIX_SOURCE && X86_FXSR_MAGIC */
+
+#ifdef WIN32
+LONG CALLBACK win32_sig_handler_sse(EXCEPTION_POINTERS* ep)
+{
+ if(ep->ExceptionRecord->ExceptionCode==EXCEPTION_ILLEGAL_INSTRUCTION){
+ // mp_msg(MSGT_CPUDETECT,MSGL_V, "SIGILL, " );
+ ep->ContextRecord->Eip +=3;
+ gCpuCaps.hasSSE=0;
+ return EXCEPTION_CONTINUE_EXECUTION;
+ }
+ return EXCEPTION_CONTINUE_SEARCH;
+}
+#endif /* WIN32 */
+
+/* If we're running on a processor that can do SSE, let's see if we
+ * are allowed to or not. This will catch 2.4.0 or later kernels that
+ * haven't been configured for a Pentium III but are running on one,
+ * and RedHat patched 2.2 kernels that have broken exception handling
+ * support for user space apps that do SSE.
+ */
+
+#if defined(__FreeBSD__) || defined(__DragonFly__)
+#define SSE_SYSCTL_NAME "hw.instruction_sse"
+#elif defined(__APPLE__)
+#define SSE_SYSCTL_NAME "hw.optional.sse"
+#endif
+
+static void check_os_katmai_support( void )
+{
+#ifdef ARCH_X86_64
+ gCpuCaps.hasSSE=1;
+ gCpuCaps.hasSSE2=1;
+#elif defined(__FreeBSD__) || defined(__DragonFly__) || defined(__APPLE__)
+ int has_sse=0, ret;
+ size_t len=sizeof(has_sse);
+
+ ret = sysctlbyname(SSE_SYSCTL_NAME, &has_sse, &len, NULL, 0);
+ if (ret || !has_sse)
+ gCpuCaps.hasSSE=0;
+
+#elif defined(__NetBSD__) || defined (__OpenBSD__)
+#if __NetBSD_Version__ >= 105250000 || (defined __OpenBSD__)
+ int has_sse, has_sse2, ret, mib[2];
+ size_t varlen;
+
+ mib[0] = CTL_MACHDEP;
+ mib[1] = CPU_SSE;
+ varlen = sizeof(has_sse);
+
+ // mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " );
+ ret = sysctl(mib, 2, &has_sse, &varlen, NULL, 0);
+ if (ret < 0 || !has_sse) {
+ gCpuCaps.hasSSE=0;
+ // mp_msg(MSGT_CPUDETECT,MSGL_V, "no!\n" );
+ } else {
+ gCpuCaps.hasSSE=1;
+ // mp_msg(MSGT_CPUDETECT,MSGL_V, "yes!\n" );
+ }
+
+ mib[1] = CPU_SSE2;
+ varlen = sizeof(has_sse2);
+ // mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE2... " );
+ ret = sysctl(mib, 2, &has_sse2, &varlen, NULL, 0);
+ if (ret < 0 || !has_sse2) {
+ gCpuCaps.hasSSE2=0;
+ // mp_msg(MSGT_CPUDETECT,MSGL_V, "no!\n" );
+ } else {
+ gCpuCaps.hasSSE2=1;
+ // mp_msg(MSGT_CPUDETECT,MSGL_V, "yes!\n" );
+ }
+#else
+ gCpuCaps.hasSSE = 0;
+ // mp_msg(MSGT_CPUDETECT,MSGL_WARN, "No OS support for SSE, disabling to be safe.\n" );
+#endif
+#elif defined(WIN32)
+ LPTOP_LEVEL_EXCEPTION_FILTER exc_fil;
+ if ( gCpuCaps.hasSSE ) {
+ // mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " );
+ exc_fil = SetUnhandledExceptionFilter(win32_sig_handler_sse);
+ __asm __volatile ("xorps %xmm0, %xmm0");
+ SetUnhandledExceptionFilter(exc_fil);
+ if ( gCpuCaps.hasSSE ) // mp_msg(MSGT_CPUDETECT,MSGL_V, "yes.\n" );
+ else // mp_msg(MSGT_CPUDETECT,MSGL_V, "no!\n" );
+ }
+#elif defined(__linux__)
+#if defined(_POSIX_SOURCE) && defined(X86_FXSR_MAGIC)
+ struct sigaction saved_sigill;
+ struct sigaction saved_sigfpe;
+
+ /* Save the original signal handlers.
+ */
+ sigaction( SIGILL, NULL, &saved_sigill );
+ sigaction( SIGFPE, NULL, &saved_sigfpe );
+
+ signal( SIGILL, (void (*)(int))sigill_handler_sse );
+ signal( SIGFPE, (void (*)(int))sigfpe_handler_sse );
+
+ /* Emulate test for OSFXSR in CR4. The OS will set this bit if it
+ * supports the extended FPU save and restore required for SSE. If
+ * we execute an SSE instruction on a PIII and get a SIGILL, the OS
+ * doesn't support Streaming SIMD Exceptions, even if the processor
+ * does.
+ */
+ if ( gCpuCaps.hasSSE ) {
+ // mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " );
+
+// __asm __volatile ("xorps %%xmm0, %%xmm0");
+ __asm __volatile ("xorps %xmm0, %xmm0");
+
+ if ( gCpuCaps.hasSSE ) {
+ // mp_msg(MSGT_CPUDETECT,MSGL_V, "yes.\n" );
+ } else {
+ // mp_msg(MSGT_CPUDETECT,MSGL_V, "no!\n" );
+ }
+ }
+
+ /* Emulate test for OSXMMEXCPT in CR4. The OS will set this bit if
+ * it supports unmasked SIMD FPU exceptions. If we unmask the
+ * exceptions, do a SIMD divide-by-zero and get a SIGILL, the OS
+ * doesn't support unmasked SIMD FPU exceptions. If we get a SIGFPE
+ * as expected, we're okay but we need to clean up after it.
+ *
+ * Are we being too stringent in our requirement that the OS support
+ * unmasked exceptions? Certain RedHat 2.2 kernels enable SSE by
+ * setting CR4.OSFXSR but don't support unmasked exceptions. Win98
+ * doesn't even support them. We at least know the user-space SSE
+ * support is good in kernels that do support unmasked exceptions,
+ * and therefore to be safe I'm going to leave this test in here.
+ */
+ if ( gCpuCaps.hasSSE ) {
+ // mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE unmasked exceptions... " );
+
+// test_os_katmai_exception_support();
+
+ if ( gCpuCaps.hasSSE ) {
+ // mp_msg(MSGT_CPUDETECT,MSGL_V, "yes.\n" );
+ } else {
+ // mp_msg(MSGT_CPUDETECT,MSGL_V, "no!\n" );
+ }
+ }
+
+ /* Restore the original signal handlers.
+ */
+ sigaction( SIGILL, &saved_sigill, NULL );
+ sigaction( SIGFPE, &saved_sigfpe, NULL );
+
+ /* If we've gotten to here and the XMM CPUID bit is still set, we're
+ * safe to go ahead and hook out the SSE code throughout Mesa.
+ */
+ if ( gCpuCaps.hasSSE ) {
+ // mp_msg(MSGT_CPUDETECT,MSGL_V, "Tests of OS support for SSE passed.\n" );
+ } else {
+ // mp_msg(MSGT_CPUDETECT,MSGL_V, "Tests of OS support for SSE failed!\n" );
+ }
+#else
+ /* We can't use POSIX signal handling to test the availability of
+ * SSE, so we disable it by default.
+ */
+ // mp_msg(MSGT_CPUDETECT,MSGL_WARN, "Cannot test OS support for SSE, disabling to be safe.\n" );
+ gCpuCaps.hasSSE=0;
+#endif /* _POSIX_SOURCE && X86_FXSR_MAGIC */
+#else
+ /* Do nothing on other platforms for now.
+ */
+ // mp_msg(MSGT_CPUDETECT,MSGL_WARN, "Cannot test OS support for SSE, leaving disabled.\n" );
+ gCpuCaps.hasSSE=0;
+#endif /* __linux__ */
+}
+#else /* ARCH_X86 || ARCH_X86_64 */
+
+#ifdef SYS_DARWIN
+#include <sys/sysctl.h>
+#else
+#ifndef __AMIGAOS4__
+#include <signal.h>
+#include <setjmp.h>
+
+static sigjmp_buf jmpbuf;
+static volatile sig_atomic_t canjump = 0;
+
+static void sigill_handler (int sig)
+{
+ if (!canjump) {
+ signal (sig, SIG_DFL);
+ raise (sig);
+ }
+
+ canjump = 0;
+ siglongjmp (jmpbuf, 1);
+}
+#endif //__AMIGAOS4__
+#endif
+
+void GetCpuCaps( CpuCaps *caps)
+{
+ caps->cpuType=0;
+ caps->cpuModel=0;
+ caps->cpuStepping=0;
+ caps->hasMMX=0;
+ caps->hasMMX2=0;
+ caps->has3DNow=0;
+ caps->has3DNowExt=0;
+ caps->hasSSE=0;
+ caps->hasSSE2=0;
+ caps->isX86=0;
+ caps->hasAltiVec = 0;
+#ifdef HAVE_ALTIVEC
+#ifdef SYS_DARWIN
+/*
+ rip-off from ffmpeg altivec detection code.
+ this code also appears on Apple's AltiVec pages.
+ */
+ {
+ int sels[2] = {CTL_HW, HW_VECTORUNIT};
+ int has_vu = 0;
+ size_t len = sizeof(has_vu);
+ int err;
+
+ err = sysctl(sels, 2, &has_vu, &len, NULL, 0);
+
+ if (err == 0)
+ if (has_vu != 0)
+ caps->hasAltiVec = 1;
+ }
+#else /* SYS_DARWIN */
+#ifdef __AMIGAOS4__
+ ULONG result = 0;
+
+ GetCPUInfoTags(GCIT_VectorUnit, &result, TAG_DONE);
+ if (result == VECTORTYPE_ALTIVEC)
+ caps->hasAltiVec = 1;
+#else
+/* no Darwin, do it the brute-force way */
+/* this is borrowed from the libmpeg2 library */
+ {
+ signal (SIGILL, sigill_handler);
+ if (sigsetjmp (jmpbuf, 1)) {
+ signal (SIGILL, SIG_DFL);
+ } else {
+ canjump = 1;
+
+ asm volatile ("mtspr 256, %0\n\t"
+ "vand %%v0, %%v0, %%v0"
+ :
+ : "r" (-1));
+
+ signal (SIGILL, SIG_DFL);
+ caps->hasAltiVec = 1;
+ }
+ }
+#endif //__AMIGAOS4__
+#endif /* SYS_DARWIN */
+ // mp_msg(MSGT_CPUDETECT,MSGL_INFO,"AltiVec %sfound\n", (caps->hasAltiVec ? "" : "not "));
+#endif /* HAVE_ALTIVEC */
+
+#ifdef ARCH_IA64
+ // mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: Intel Itanium\n");
+#endif
+
+#ifdef ARCH_SPARC
+ // mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: Sun Sparc\n");
+#endif
+
+#ifdef ARCH_ARMV4L
+ // mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: ARM\n");
+#endif
+
+#ifdef ARCH_POWERPC
+ // mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: PowerPC\n");
+#endif
+
+#ifdef ARCH_ALPHA
+ // mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: Digital Alpha\n");
+#endif
+
+#ifdef ARCH_SGI_MIPS
+ // mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: SGI MIPS\n");
+#endif
+
+#ifdef ARCH_PA_RISC
+ // mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: Hewlett-Packard PA-RISC\n");
+#endif
+
+#ifdef ARCH_S390
+ // mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: IBM S/390\n");
+#endif
+
+#ifdef ARCH_S390X
+ // mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: IBM S/390X\n");
+#endif
+
+#ifdef ARCH_VAX
+ // mp_msg(MSGT_CPUDETECT,MSGL_INFO, "CPU: Digital VAX\n" );
+#endif
+}
+#endif /* !ARCH_X86 */
Added: vic/branches/mpeg4/cpu/cpudetect.h
==============================================================================
--- (empty file)
+++ vic/branches/mpeg4/cpu/cpudetect.h Thu Nov 16 10:26:25 2006
@@ -0,0 +1,79 @@
+#ifndef CPUDETECT_H
+#define CPUDETECT_H
+
+#include "config_arch.h"
+
+#define CPUTYPE_I386 3
+#define CPUTYPE_I486 4
+#define CPUTYPE_I586 5
+#define CPUTYPE_I686 6
+
+#ifdef ARCH_X86_64
+# define REGa rax
+# define REGb rbx
+# define REGBP rbp
+# define REGSP rsp
+# define REG_a "rax"
+# define REG_b "rbx"
+# define REG_c "rcx"
+# define REG_d "rdx"
+# define REG_S "rsi"
+# define REG_D "rdi"
+# define REG_SP "rsp"
+# define REG_BP "rbp"
+#else
+# define REGa eax
+# define REGb ebx
+# define REGBP ebp
+# define REGSP esp
+# define REG_a "eax"
+# define REG_b "ebx"
+# define REG_c "ecx"
+# define REG_d "edx"
+# define REG_S "esi"
+# define REG_D "edi"
+# define REG_SP "esp"
+# define REG_BP "ebp"
+#endif
+
+typedef struct cpucaps_s {
+ int cpuType;
+ int cpuModel;
+ int cpuStepping;
+ int hasMMX;
+ int hasMMX2;
+ int has3DNow;
+ int has3DNowExt;
+ int hasSSE;
+ int hasSSE2;
+ int isX86;
+ unsigned cl_size; /* size of cache line */
+ int hasAltiVec;
+ int hasTSC;
+ char cpuname[50];
+} CpuCaps;
+
+enum
+{
+ FF_CPU_MMX =0x00000001,
+ FF_CPU_MMXEXT =0x00000002,
+ FF_CPU_SSE =0x00000004,
+ FF_CPU_SSE2 =0x00000008,
+ FF_CPU_3DNOW =0x00000010,
+ FF_CPU_3DNOWEXT=0x00000020,
+ FF_CPU_ALTIVEC =0x00000040,
+};
+
+/* return available_cpu_flags defined above */
+int cpu_check();
+
+extern CpuCaps gCpuCaps;
+void GetCpuCaps(CpuCaps *caps);
+
+/* returned value is malloc()'ed so free() it after use */
+char *GetCpuFriendlyName(unsigned int regs[], unsigned int regs2[]);
+
+
+
+#endif /* !CPUDETECT_H */
+
Added: vic/branches/mpeg4/cpu/cpuid.asm
==============================================================================
--- (empty file)
+++ vic/branches/mpeg4/cpu/cpuid.asm Thu Nov 16 10:26:25 2006
@@ -0,0 +1,199 @@
+;/****************************************************************************
+; *
+; * XVID MPEG-4 VIDEO CODEC
+; * - CPUID check processors capabilities -
+; *
+; * Copyright (C) 2001 Michael Militzer <isibaar at xvid.org>
+; *
+; * This program is free software ; you can redistribute it and/or modify
+; * it under the terms of the GNU General Public License as published by
+; * the Free Software Foundation ; either version 2 of the License, or
+; * (at your option) any later version.
+; *
+; * This program is distributed in the hope that it will be useful,
+; * but WITHOUT ANY WARRANTY ; without even the implied warranty of
+; * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+; * GNU General Public License for more details.
+; *
+; * You should have received a copy of the GNU General Public License
+; * along with this program ; if not, write to the Free Software
+; * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+; *
+; ***************************************************************************/
+
+BITS 32
+
+%macro cglobal 1
+ %ifdef PREFIX
+ global _%1
+ %define %1 _%1
+ %else
+ global %1
+ %endif
+%endmacro
+
+;=============================================================================
+; Constants
+;=============================================================================
+
+%define CPUID_TSC 0x00000010
+%define CPUID_MMX 0x00800000
+%define CPUID_SSE 0x02000000
+%define CPUID_SSE2 0x04000000
+
+%define EXT_CPUID_3DNOW 0x80000000
+%define EXT_CPUID_AMD_3DNOWEXT 0x40000000
+%define EXT_CPUID_AMD_MMXEXT 0x00400000
+
+%define FF_CPU_MMX 0x00000001
+%define FF_CPU_MMXEXT 0x00000002
+%define FF_CPU_SSE 0x00000004
+%define FF_CPU_SSE2 0x00000008
+%define FF_CPU_3DNOW 0x00000010
+%define FF_CPU_3DNOWEXT 0x00000020
+%define FF_CPU_TSC 0x00000040
+
+;=============================================================================
+; Read only data
+;=============================================================================
+
+ALIGN 32
+%ifdef FORMAT_COFF
+SECTION .rodata data
+%else
+SECTION .rodata data align=16
+%endif
+
+vendorAMD:
+ db "AuthenticAMD"
+
+;=============================================================================
+; Macros
+;=============================================================================
+
+%macro CHECK_FEATURE 3
+ mov ecx, %1
+ and ecx, edx
+ neg ecx
+ sbb ecx, ecx
+ and ecx, %2
+ or %3, ecx
+%endmacro
+
+;=============================================================================
+; Code
+;=============================================================================
+
+SECTION .text
+
+; int check_cpu_feature(void)
+
+cglobal check_cpu_features
+check_cpu_features:
+
+ push ebx
+ push esi
+ push edi
+ push ebp
+
+ sub esp, 12 ; Stack space for vendor name
+
+ xor ebp,ebp
+
+ ; CPUID command ?
+ pushfd
+ pop eax
+ mov ecx, eax
+ xor eax, 0x200000
+ push eax
+ popfd
+ pushfd
+ pop eax
+ cmp eax, ecx
+
+ jz near .cpu_quit ; no CPUID command -> exit
+
+
+ ; get vendor string, used later
+ xor eax, eax
+ cpuid
+ mov [esp], ebx ; vendor string
+ mov [esp+4], edx
+ mov [esp+8], ecx
+ test eax, eax
+
+ jz near .cpu_quit
+
+ mov eax, 1
+ cpuid
+
+ ; RDTSC command ?
+ CHECK_FEATURE CPUID_TSC, FF_CPU_TSC, ebp
+
+ ; MMX support ?
+ CHECK_FEATURE CPUID_MMX, FF_CPU_MMX, ebp
+
+ ; SSE support ?
+ CHECK_FEATURE CPUID_SSE, (FF_CPU_MMXEXT|FF_CPU_SSE), ebp
+
+ ; SSE2 support?
+ CHECK_FEATURE CPUID_SSE2, FF_CPU_SSE2, ebp
+
+ ; extended functions?
+ mov eax, 0x80000000
+ cpuid
+ cmp eax, 0x80000000
+ jbe near .cpu_quit
+
+ mov eax, 0x80000001
+ cpuid
+
+ ; AMD cpu ?
+ lea esi, [vendorAMD]
+ lea edi, [esp]
+ mov ecx, 12
+ cld
+ repe cmpsb
+ jnz .cpu_quit
+
+ ; 3DNow! support ?
+ CHECK_FEATURE EXT_CPUID_3DNOW, FF_CPU_3DNOW, ebp
+
+ ; 3DNOW extended ?
+ CHECK_FEATURE EXT_CPUID_AMD_3DNOWEXT, FF_CPU_3DNOWEXT, ebp
+
+ ; extended MMX ?
+ CHECK_FEATURE EXT_CPUID_AMD_MMXEXT, FF_CPU_MMXEXT, ebp
+
+.cpu_quit:
+
+ mov eax, ebp
+
+ add esp, 12
+
+ pop ebp
+ pop edi
+ pop esi
+ pop ebx
+
+ ret
+.endfunc
+
+; sse/sse2 operating support detection routines
+; these will trigger an invalid instruction signal if not supported.
+ALIGN 16
+cglobal sse_os_trigger
+sse_os_trigger:
+ xorps xmm0, xmm0
+ ret
+.endfunc
+
+
+ALIGN 16
+cglobal sse2_os_trigger
+sse2_os_trigger:
+ xorpd xmm0, xmm0
+ ret
+.endfunc
+
+
Added: vic/branches/mpeg4/cpu/cpuid.cpp
==============================================================================
--- (empty file)
+++ vic/branches/mpeg4/cpu/cpuid.cpp Thu Nov 16 10:26:25 2006
@@ -0,0 +1,102 @@
+#if defined(WIN32) || defined(WIN64)
+#include <windows.h>
+#endif
+
+extern "C"{
+#include "cpu/cpudetect.h"
+}
+#include <stdio.h>
+
+static CpuCaps aCpuCaps;
+static int available_cpu_flags;
+
+#ifndef WIN64
+extern "C"
+{
+ // cpu_flag detection helper functions
+ extern int check_cpu_features(void);
+ extern void sse_os_trigger(void);
+ extern void sse2_os_trigger(void);
+}
+
+
+ #ifdef __GNUC__
+ #include <signal.h>
+ #include <setjmp.h>
+ static jmp_buf mark;
+ static void sigill_handler(int signal)
+ {
+ longjmp(mark, 1);
+ }
+ static int sigill_check(void (*func)())
+ {
+ void (*old_handler)(int);
+ int jmpret;
+ old_handler=signal(SIGILL,sigill_handler);
+ if (old_handler==SIG_ERR)
+ return -1;
+
+ jmpret=setjmp(mark);
+ if (jmpret==0)
+ func();
+ signal(SIGILL,old_handler);
+ return jmpret;
+ }
+ #else
+ static int sigill_check(void (*func)())
+ {
+ __try
+ {
+ func();
+ }
+ __except(EXCEPTION_EXECUTE_HANDLER)
+ {
+ if (_exception_code()==STATUS_ILLEGAL_INSTRUCTION)
+ return 1;
+ }
+ return 0;
+ }
+ #endif
+#endif
+
+
+int cpu_check(){
+
+#ifdef __GNUC__
+ /* CPU capabilities detection */
+ GetCpuCaps(&aCpuCaps);
+ available_cpu_flags=(aCpuCaps.hasMMX ? FF_CPU_MMX|FF_CPU_MMXEXT:0)|
+ (aCpuCaps.has3DNow ? FF_CPU_3DNOW|FF_CPU_3DNOWEXT:0)|
+ (aCpuCaps.hasSSE ? FF_CPU_SSE:0)|
+ (aCpuCaps.hasSSE2 ? FF_CPU_SSE2:0);
+
+#elif defined(WIN32)
+ available_cpu_flags=check_cpu_features();
+ if ((available_cpu_flags&FF_CPU_SSE) && sigill_check(sse_os_trigger))
+ available_cpu_flags&=~FF_CPU_SSE;
+ if ((available_cpu_flags&FF_CPU_SSE2) && sigill_check(sse2_os_trigger))
+ available_cpu_flags&=~FF_CPU_SSE2;
+
+#elif defined(WIN64)
+ available_cpu_flags=(IsProcessorFeaturePresent(PF_MMX_INSTRUCTIONS_AVAILABLE)?FF_CPU_MMX|FF_CPU_MMXEXT:0)|
+ (IsProcessorFeaturePresent(PF_3DNOW_INSTRUCTIONS_AVAILABLE)?FF_CPU_3DNOW|FF_CPU_3DNOWEXT:0)|
+ (IsProcessorFeaturePresent(PF_XMMI_INSTRUCTIONS_AVAILABLE)?FF_CPU_SSE:0)|
+ (IsProcessorFeaturePresent(PF_XMMI64_INSTRUCTIONS_AVAILABLE)?FF_CPU_SSE2:0);
+ #ifdef __INTEL_COMPILER
+ available_cpu_flags|=FF_CPU_MMX|FF_CPU_MMXEXT;
+ #endif
+
+#endif
+
+ aCpuCaps.hasMMX = (available_cpu_flags & FF_CPU_MMX ? 1:0);
+ aCpuCaps.hasMMX2 = (available_cpu_flags & FF_CPU_MMXEXT ? 1:0);
+ aCpuCaps.hasSSE = (available_cpu_flags & FF_CPU_SSE ? 1:0);
+ aCpuCaps.hasSSE2 = (available_cpu_flags & FF_CPU_SSE2 ? 1:0);
+ aCpuCaps.has3DNow = (available_cpu_flags & FF_CPU_3DNOW ? 1:0);
+ aCpuCaps.has3DNowExt = (available_cpu_flags & FF_CPU_3DNOWEXT ? 1:0);
+
+ printf("cpudetect: MMX=%d MMX2=%d SSE=%d SSE2=%d 3DNow=%d 3DNowExt=%d\n", \
+ aCpuCaps.hasMMX, aCpuCaps.hasMMX2, aCpuCaps.hasSSE, aCpuCaps.hasSSE2, \
+ aCpuCaps.has3DNow, aCpuCaps.has3DNowExt );
+ return available_cpu_flags;
+}
\ No newline at end of file
Added: vic/branches/mpeg4/cpu/cputable.h
==============================================================================
--- (empty file)
+++ vic/branches/mpeg4/cpu/cputable.h Thu Nov 16 10:26:25 2006
@@ -0,0 +1,528 @@
+/* cputable.h - Maps CPUID to real CPU name.
+ * Copyleft 2001 by Felix Buenemann <atmosfear at users dot sourceforge dot net>
+ * This file comes under the GNU GPL, see www.fsf.org for more info!
+ * Family F codenames owe much thanks to Neil Phillips, author of x86test.
+ */
+
+#define MAX_VENDORS 8 /* Number of CPU Vendors */
+
+//#define N_UNKNOWN "unknown"
+//#define N_UNKNOWNEXT "unknown extended model"
+#define N_UNKNOWN ""
+#define N_UNKNOWNEXT ""
+
+#define F_UNKNOWN { \
+N_UNKNOWN, \
+N_UNKNOWN, \
+N_UNKNOWN, \
+N_UNKNOWN, \
+N_UNKNOWN, \
+N_UNKNOWN, \
+N_UNKNOWN, \
+N_UNKNOWN, \
+N_UNKNOWN, \
+N_UNKNOWN, \
+N_UNKNOWN, \
+N_UNKNOWN, \
+N_UNKNOWN, \
+N_UNKNOWN, \
+N_UNKNOWN, \
+N_UNKNOWN \
+}
+
+static const char *cpuname
+ /* Vendor */ [MAX_VENDORS]
+ /* Family */ [16]
+ /* Model */ [16]
+ ={
+ /* Intel Corporation, "GenuineIntel" */ {
+ /* 0 */ F_UNKNOWN,
+ /* 1 */ F_UNKNOWN,
+ /* 2 */ F_UNKNOWN,
+ /* 3 i386 */ F_UNKNOWN, /* XXX new 386 chips may support CPUID! */
+ /* 4 i486 */ {
+ /* 0 */ "i486DX-25/33", /* only few of these */
+ /* 1 */ "i486DX-50", /* support CPUID! */
+ /* 2 */ "i486SX",
+ /* 3 */ "i486DX2", /* CPUID only on new chips! */
+ /* 4 */ "i486SL",
+ /* 5 */ "i486SX2",
+ /* 6 */ N_UNKNOWN,
+ /* 7 */ "i486DX2/write-back", /* returns 3 in write-through mode */
+ /* 8 */ "i486DX4",
+ /* 9 */ "i486DX4/write-back",
+ /* A */ N_UNKNOWN,
+ /* B */ N_UNKNOWN,
+ /* C */ N_UNKNOWN,
+ /* D */ N_UNKNOWN,
+ /* E */ N_UNKNOWN,
+ /* F */ N_UNKNOWNEXT
+ },
+ /* 5 i586 */ {
+ /* 0 */ "Pentium P5 A-step",
+ /* 1 */ "Pentium P5",
+ /* 2 */ "Pentium P54C",
+ /* 3 */ "Pentium OverDrive P24T",
+ /* 4 */ "Pentium MMX P55C",
+ /* 5 */ N_UNKNOWN, /* XXX DX4 OverDrive? */
+ /* 6 */ N_UNKNOWN, /* XXX P5 OverDrive? */
+ /* 7 */ "Pentium P54C (new)",
+ /* 8 */ "Pentium MMX P55C (new)",
+ /* 9 */ N_UNKNOWN,
+ /* A */ N_UNKNOWN,
+ /* B */ N_UNKNOWN,
+ /* C */ N_UNKNOWN,
+ /* D */ N_UNKNOWN,
+ /* E */ N_UNKNOWN,
+ /* F */ N_UNKNOWNEXT
+ },
+ /* 6 i686 */ {
+ /* 0 */ "PentiumPro A-step",
+ /* 1 */ "PentiumPro",
+ /* 2 */ N_UNKNOWN,
+ /* 3 */ "Pentium II Klamath/Pentium II OverDrive",
+ /* 4 */ N_UNKNOWN, /* XXX P55CT - OverDrive for P54? */
+ /* 5 */ "Celeron Covington/Pentium II Deschutes,Tonga/Pentium II Xeon",
+ /* 6 */ "Celeron A Mendocino/Pentium II Dixon",
+ /* 7 */ "Pentium III Katmai/Pentium III Xeon Tanner",
+ /* 8 */ "Celeron 2/Pentium III Coppermine,Geyserville",
+ /* 9 */ "Pentium M Banias", /* XXX check */
+ /* A */ "Pentium III Xeon Cascades",
+ /* B */ "Celeron 2/Pentium III Tualatin",
+ /* C */ N_UNKNOWN,
+ /* D */ "Pentium M Dothan",
+ /* E */ N_UNKNOWN,
+ /* F */ N_UNKNOWNEXT
+ },
+ /* 7 Itanium */ { /* XXX check */
+ /* 0 */ "Itanium Merced",
+ /* 1 */ N_UNKNOWN,
+ /* 2 */ N_UNKNOWN,
+ /* 3 */ N_UNKNOWN,
+ /* 4 */ N_UNKNOWN,
+ /* 5 */ N_UNKNOWN,
+ /* 6 */ N_UNKNOWN,
+ /* 7 */ N_UNKNOWN,
+ /* 8 */ N_UNKNOWN,
+ /* 9 */ N_UNKNOWN,
+ /* A */ N_UNKNOWN,
+ /* B */ N_UNKNOWN,
+ /* C */ N_UNKNOWN,
+ /* D */ N_UNKNOWN,
+ /* E */ N_UNKNOWN,
+ /* F */ N_UNKNOWNEXT
+ },
+ /* 8 */ F_UNKNOWN,
+ /* 9 */ F_UNKNOWN,
+ /* A */ F_UNKNOWN,
+ /* B */ F_UNKNOWN,
+ /* C */ F_UNKNOWN,
+ /* D */ F_UNKNOWN,
+ /* E */ F_UNKNOWN,
+ /* F extended family (P4/new IA-64)*/ {
+ /* 0 */ "Pentium 4 Willamette; Xeon Foster",
+ /* 1 */ "Pentium 4 Willamette; Xeon Foster",
+ /* 2 */ "Pentium 4/Celeron 4 Northwood; Pentium 4 EE/Xeon Prestonia,Gallatin",
+ /* 3 */ "Pentium 4/Celeron D Prescott; Xeon Nocona",
+ /* 4 */ "Pentium 4/Celeron D Prescott; Pentium D/XE Smithfield; Xeon Nocona,Irwindale",
+ /* 5 */ N_UNKNOWN,
+ /* 6 */ N_UNKNOWN,
+ /* 7 */ N_UNKNOWN,
+ /* 8 */ N_UNKNOWN,
+ /* 9 */ N_UNKNOWN,
+ /* A */ N_UNKNOWN,
+ /* B */ N_UNKNOWN,
+ /* C */ N_UNKNOWN,
+ /* D */ N_UNKNOWN,
+ /* E */ N_UNKNOWN,
+ /* F */ N_UNKNOWNEXT
+ }
+ #if 0 /* out of table index boundaries */
+ /* 1F Itanium 2 */ { /* XXX check */
+ /* 0 */ "Itanium 2 McKinley",
+ /* 1 */ "Itanium 2 Madison", /* I coded on that :-) */
+ /* 2 */ N_UNKNOWN,
+ /* 3 */ N_UNKNOWN,
+ /* 4 */ N_UNKNOWN,
+ /* 5 */ N_UNKNOWN,
+ /* 6 */ N_UNKNOWN,
+ /* 7 */ N_UNKNOWN,
+ /* 8 */ N_UNKNOWN,
+ /* 9 */ N_UNKNOWN,
+ /* A */ N_UNKNOWN,
+ /* B */ N_UNKNOWN,
+ /* C */ N_UNKNOWN,
+ /* D */ N_UNKNOWN,
+ /* E */ N_UNKNOWN,
+ /* F */ N_UNKNOWNEXT
+ },
+ #endif
+ },
+ /* United Microelectronics Corporation, "UMC UMC UMC " */ {
+ /* 0 */ F_UNKNOWN,
+ /* 1 */ F_UNKNOWN,
+ /* 2 */ F_UNKNOWN,
+ /* 3 */ F_UNKNOWN,
+ /* 4 486 (U5) */ {
+ /* 0 */ N_UNKNOWN,
+ /* 1 */ "486DX U5D",
+ /* 2 */ "486SX U5S",
+ /* 3 */ N_UNKNOWN,
+ /* 4 */ N_UNKNOWN,
+ /* 5 */ N_UNKNOWN,
+ /* 6 */ N_UNKNOWN,
+ /* 7 */ N_UNKNOWN,
+ /* 8 */ N_UNKNOWN,
+ /* 9 */ N_UNKNOWN,
+ /* A */ N_UNKNOWN,
+ /* B */ N_UNKNOWN,
+ /* C */ N_UNKNOWN,
+ /* D */ N_UNKNOWN,
+ /* E */ N_UNKNOWN,
+ /* F */ N_UNKNOWN
+ },
+ /* 5 */ F_UNKNOWN,
+ /* 6 */ F_UNKNOWN,
+ /* 7 */ F_UNKNOWN,
+ /* 8 */ F_UNKNOWN,
+ /* 9 */ F_UNKNOWN,
+ /* A */ F_UNKNOWN,
+ /* B */ F_UNKNOWN,
+ /* C */ F_UNKNOWN,
+ /* D */ F_UNKNOWN,
+ /* E */ F_UNKNOWN,
+ /* F */ F_UNKNOWN
+ },
+ /* Advanced Micro Devices, "AuthenticAMD" (very rare: "AMD ISBETTER") */ {
+ /* 0 */ F_UNKNOWN,
+ /* 1 */ F_UNKNOWN,
+ /* 2 */ F_UNKNOWN,
+ /* 3 */ F_UNKNOWN,
+ /* 4 486/5x86 */ {
+ /* 0 */ N_UNKNOWN,
+ /* 1 */ N_UNKNOWN,
+ /* 2 */ N_UNKNOWN,
+ /* 3 */ "486DX2",
+ /* 4 */ N_UNKNOWN,
+ /* 5 */ N_UNKNOWN,
+ /* 6 */ N_UNKNOWN,
+ /* 7 */ "486DX2/write-back",
+ /* 8 */ "486DX4/5x86",
+ /* 9 */ "486DX4/write-back",
+ /* A */ N_UNKNOWN,
+ /* B */ N_UNKNOWN,
+ /* C */ N_UNKNOWN,
+ /* D */ N_UNKNOWN,
+ /* E */ "5x86",
+ /* F */ "5x86/write-back"
+ },
+ /* 5 K5/K6 */ {
+ /* 0 */ "K5 SSA5 (PR75,PR90,PR100)",
+ /* 1 */ "K5 5k86 (PR120,PR133)",
+ /* 2 */ "K5 5k86 (PR166)",
+ /* 3 */ "K5 5k86 (PR200)",
+ /* 4 */ N_UNKNOWN,
+ /* 5 */ N_UNKNOWN,
+ /* 6 */ "K6",
+ /* 7 */ "K6 Little Foot",
+ /* 8 */ "K6-2",
+ /* 9 */ "K6-III Chomper",
+ /* A */ N_UNKNOWN,
+ /* B */ N_UNKNOWN,
+ /* C */ N_UNKNOWN,
+ /* D */ "K6-2+/K6-III+ Sharptooth",
+ /* E */ N_UNKNOWN,
+ /* F */ N_UNKNOWN
+ },
+ /* 6 K7 */ {
+ /* 0 */ N_UNKNOWN, /* Argon? */
+ /* 1 */ "Athlon K7",
+ /* 2 */ "Athlon K75 Pluto,Orion",
+ /* 3 */ "Duron Spitfire",
+ /* 4 */ "Athlon Thunderbird",
+ /* 5 */ N_UNKNOWN,
+ /* 6 */ "Duron/Athlon 4/MP/XP Palomino",
+ /* 7 */ "Duron Morgan,Camaro",
+ /* 8 */ "Sempron/Athlon MP/XP Thoroughbred; Duron Applebred",
+ /* 9 */ N_UNKNOWN,
+ /* A */ "Sempron/Athlon MP/XP/XP-M Barton,Thorton",
+ /* B */ N_UNKNOWN,
+ /* E */ N_UNKNOWN,
+ /* C */ N_UNKNOWN,
+ /* D */ N_UNKNOWN,
+ /* F */ N_UNKNOWN
+ },
+ /* 7 */ F_UNKNOWN,
+ /* 8 */ F_UNKNOWN,
+ /* 9 */ F_UNKNOWN,
+ /* A */ F_UNKNOWN,
+ /* B */ F_UNKNOWN,
+ /* C */ F_UNKNOWN,
+ /* D */ F_UNKNOWN,
+ /* E */ F_UNKNOWN,
+ /* F K8 */ {
+ /* 0 */ N_UNKNOWN,
+ /* 1 */ "Opteron Egypt,Italy,Denmark",
+ /* 2 */ N_UNKNOWN,
+ /* 3 */ "Athlon 64 X2 Manchester,Toledo",
+ /* 4 */ "Athlon 64 Clawhammer; Athlon 64 X2 Toledo; Turion Newark,Lancaster",
+ /* 5 */ "Athlon 64 FX/Opteron Sledgehammer,Athens,Troy,Venus",
+ /* 6 */ N_UNKNOWN,
+ /* 7 */ "Athlon 64/FX Sledgehammer,San Diego,Venice",
+ /* 8 */ "Mobile Athlon 64 Newcastle; Mobile Sempron Dublin",
+ /* 9 */ N_UNKNOWN,
+ /* A */ N_UNKNOWN,
+ /* B */ "Athlon 64 Newcastle; Athlon 64 X2 Manchester",
+ /* E */ N_UNKNOWN,
+ /* C */ "Athlon 64 Newcastle,Odesssa,Oakville,Venice; Sempron Palermo,Paris,Dublin",
+ /* D */ N_UNKNOWN,
+ /* F */ "Athlon 64 Newcastle,Winchester,San Diego,Venice; Sempron Palermo"
+ }
+
+ },
+ /* Cyrix Corp./VIA Inc., "CyrixInstead" */ {
+ /* 0 */ F_UNKNOWN,
+ /* 1 */ F_UNKNOWN,
+ /* 2 */ F_UNKNOWN,
+ /* 3 */ F_UNKNOWN,
+ /* 4 5x86 */ {
+ /* 0 */ N_UNKNOWN,
+ /* 1 */ N_UNKNOWN,
+ /* 2 */ N_UNKNOWN,
+ /* 3 */ N_UNKNOWN,
+ /* 4 */ "MediaGX",
+ /* 5 */ N_UNKNOWN,
+ /* 6 */ N_UNKNOWN,
+ /* 7 */ N_UNKNOWN,
+ /* 8 */ N_UNKNOWN,
+ /* 9 */ "5x86", /* CPUID maybe only on newer chips */
+ /* A */ N_UNKNOWN,
+ /* B */ N_UNKNOWN,
+ /* E */ N_UNKNOWN,
+ /* C */ N_UNKNOWN,
+ /* D */ N_UNKNOWN,
+ /* F */ N_UNKNOWN
+ },
+ /* 5 M1 */ {
+ /* 0 */ "M1 test-sample", /*?*/
+ /* 1 */ N_UNKNOWN,
+ /* 2 */ "6x86 M1",
+ /* 3 */ "6x86L M1",
+ /* 4 */ "GXm",
+ /* 5 */ N_UNKNOWN,
+ /* 6 */ N_UNKNOWN,
+ /* 7 */ N_UNKNOWN,
+ /* 8 */ N_UNKNOWN,
+ /* 9 */ N_UNKNOWN,
+ /* A */ N_UNKNOWN,
+ /* B */ N_UNKNOWN,
+ /* E */ N_UNKNOWN,
+ /* C */ N_UNKNOWN,
+ /* D */ N_UNKNOWN,
+ /* F */ N_UNKNOWN
+ },
+ /* 6 M2 */ {
+ /* 0 */ "6x86MX M2/M-II",
+ /* 1 */ N_UNKNOWN,
+ /* 2 */ N_UNKNOWN,
+ /* 3 */ N_UNKNOWN,
+ /* 4 */ N_UNKNOWN,
+ /* 5 */ "Cyrix III Joshua (M2 core)",
+ /* 6 */ N_UNKNOWN,
+ /* 7 */ N_UNKNOWN,
+ /* 8 */ N_UNKNOWN,
+ /* 9 */ N_UNKNOWN,
+ /* A */ N_UNKNOWN,
+ /* B */ N_UNKNOWN,
+ /* E */ N_UNKNOWN,
+ /* C */ N_UNKNOWN,
+ /* D */ N_UNKNOWN,
+ /* F */ N_UNKNOWN
+ },
+ /* 7 */ F_UNKNOWN,
+ /* 8 */ F_UNKNOWN,
+ /* 9 */ F_UNKNOWN,
+ /* A */ F_UNKNOWN,
+ /* B */ F_UNKNOWN,
+ /* C */ F_UNKNOWN,
+ /* D */ F_UNKNOWN,
+ /* E */ F_UNKNOWN,
+ /* F */ F_UNKNOWN
+ },
+ /* NexGen Inc., "NexGenDriven" */ {
+ /* 0 */ F_UNKNOWN,
+ /* 1 */ F_UNKNOWN,
+ /* 2 */ F_UNKNOWN,
+ /* 3 */ F_UNKNOWN,
+ /* 4 */ F_UNKNOWN,
+ /* 5 Nx586 */ {
+ /* 0 */ "Nx586/Nx586FPU", /* only newer ones support CPUID! */
+ /* 1 */ N_UNKNOWN,
+ /* 2 */ N_UNKNOWN,
+ /* 3 */ N_UNKNOWN,
+ /* 4 */ N_UNKNOWN,
+ /* 5 */ N_UNKNOWN,
+ /* 6 */ N_UNKNOWN,
+ /* 7 */ N_UNKNOWN,
+ /* 8 */ N_UNKNOWN,
+ /* 9 */ N_UNKNOWN,
+ /* A */ N_UNKNOWN,
+ /* B */ N_UNKNOWN,
+ /* E */ N_UNKNOWN,
+ /* C */ N_UNKNOWN,
+ /* D */ N_UNKNOWN,
+ /* F */ N_UNKNOWN
+ },
+ /* 6 */ F_UNKNOWN,
+ /* 7 */ F_UNKNOWN,
+ /* 8 */ F_UNKNOWN,
+ /* 9 */ F_UNKNOWN,
+ /* A */ F_UNKNOWN,
+ /* B */ F_UNKNOWN,
+ /* C */ F_UNKNOWN,
+ /* D */ F_UNKNOWN,
+ /* E */ F_UNKNOWN,
+ /* F */ F_UNKNOWN
+ },
+ /* IDT/Centaur/VIA, "CentaurHauls" */ {
+ /* 0 */ F_UNKNOWN,
+ /* 1 */ F_UNKNOWN,
+ /* 2 */ F_UNKNOWN,
+ /* 3 */ F_UNKNOWN,
+ /* 4 */ F_UNKNOWN,
+ /* 5 IDT C6 WinChip */ {
+ /* 0 */ N_UNKNOWN,
+ /* 1 */ N_UNKNOWN,
+ /* 2 */ N_UNKNOWN,
+ /* 3 */ N_UNKNOWN,
+ /* 4 */ "WinChip C6",
+ /* 5 */ N_UNKNOWN,
+ /* 6 */ "Samuel",
+ /* 7 */ N_UNKNOWN,
+ /* 8 */ "WinChip 2 C6+,W2,W2A,W2B",
+ /* 9 */ "WinChip 3 W3",
+ /* A */ "WinChip 4 W4A", /* XXX check */
+ /* B */ N_UNKNOWN,
+ /* E */ N_UNKNOWN,
+ /* C */ N_UNKNOWN,
+ /* D */ N_UNKNOWN,
+ /* F */ N_UNKNOWN
+ },
+ /* 6 VIA C3 */ {
+ /* 0 */ N_UNKNOWN,
+ /* 1 */ N_UNKNOWN,
+ /* 2 */ N_UNKNOWN,
+ /* 3 */ N_UNKNOWN,
+ /* 4 */ N_UNKNOWN,
+ /* 5 */ N_UNKNOWN,
+ /* 6 */ "Cyrix III Samuel (WinChip C5A core)",
+ /* 7 */ "C3 Samuel 2 (WinChip C5B core)/C3 Ezra",
+ /* 8 */ "C3 Ezra-T",
+ /* 9 */ "C3 Nehemiah",
+ /* A */ N_UNKNOWN,
+ /* B */ N_UNKNOWN,
+ /* E */ N_UNKNOWN,
+ /* C */ N_UNKNOWN,
+ /* D */ N_UNKNOWN,
+ /* F */ N_UNKNOWN
+ },
+ /* 7 */ F_UNKNOWN,
+ /* 8 */ F_UNKNOWN,
+ /* 9 */ F_UNKNOWN,
+ /* A */ F_UNKNOWN,
+ /* B */ F_UNKNOWN,
+ /* C */ F_UNKNOWN,
+ /* D */ F_UNKNOWN,
+ /* E */ F_UNKNOWN,
+ /* F */ F_UNKNOWN
+ },
+ /* Rise, "RiseRiseRise" */ {
+ /* 0 */ F_UNKNOWN,
+ /* 1 */ F_UNKNOWN,
+ /* 2 */ F_UNKNOWN,
+ /* 3 */ F_UNKNOWN,
+ /* 4 */ F_UNKNOWN,
+ /* 5 mP6 */ {
+ /* 0 */ "mP6 iDragon 6401,6441 Kirin",
+ /* 1 */ "mP6 iDragon 6510 Lynx",
+ /* 2 */ N_UNKNOWN,
+ /* 3 */ N_UNKNOWN,
+ /* 4 */ N_UNKNOWN,
+ /* 5 */ N_UNKNOWN,
+ /* 6 */ N_UNKNOWN,
+ /* 7 */ N_UNKNOWN,
+ /* 8 */ "mP6 iDragon II",
+ /* 9 */ "mP6 iDragon II (new)",
+ /* A */ N_UNKNOWN,
+ /* B */ N_UNKNOWN,
+ /* E */ N_UNKNOWN,
+ /* C */ N_UNKNOWN,
+ /* D */ N_UNKNOWN,
+ /* F */ N_UNKNOWN
+ },
+ /* 6 */ F_UNKNOWN,
+ /* 7 */ F_UNKNOWN,
+ /* 8 */ F_UNKNOWN,
+ /* 9 */ F_UNKNOWN,
+ /* A */ F_UNKNOWN,
+ /* B */ F_UNKNOWN,
+ /* C */ F_UNKNOWN,
+ /* D */ F_UNKNOWN,
+ /* E */ F_UNKNOWN,
+ /* F */ F_UNKNOWN
+ },
+ /* Transmeta, "GenuineTMx86" */ {
+ /* 0 */ F_UNKNOWN,
+ /* 1 */ F_UNKNOWN,
+ /* 2 */ F_UNKNOWN,
+ /* 3 */ F_UNKNOWN,
+ /* 4 */ F_UNKNOWN,
+ /* 5 Crusoe */ {
+ /* 0 */ N_UNKNOWN,
+ /* 1 */ N_UNKNOWN,
+ /* 2 */ N_UNKNOWN,
+ /* 3 */ N_UNKNOWN,
+ /* 4 */ "Crusoe TM3x00,TM5x00",
+ /* 5 */ N_UNKNOWN,
+ /* 6 */ N_UNKNOWN,
+ /* 7 */ N_UNKNOWN,
+ /* 8 */ N_UNKNOWN,
+ /* 9 */ N_UNKNOWN,
+ /* A */ N_UNKNOWN,
+ /* B */ N_UNKNOWN,
+ /* E */ N_UNKNOWN,
+ /* C */ N_UNKNOWN,
+ /* D */ N_UNKNOWN,
+ /* F */ N_UNKNOWN
+ },
+ /* 6 */ F_UNKNOWN,
+ /* 7 */ F_UNKNOWN,
+ /* 8 */ F_UNKNOWN,
+ /* 9 */ F_UNKNOWN,
+ /* A */ F_UNKNOWN,
+ /* B */ F_UNKNOWN,
+ /* C */ F_UNKNOWN,
+ /* D */ F_UNKNOWN,
+ /* E */ F_UNKNOWN,
+ /* F */ F_UNKNOWN
+ }
+};
+
+#undef N_UNKNOWNEXT
+#undef N_UNKNOWN
+#undef F_UNKNOWN
+
+static const struct {
+ char string[13];
+ char name[48];
+} cpuvendors[MAX_VENDORS] ={
+ {"GenuineIntel","Intel"},
+ {"UMC UMC UMC ","United Microelectronics Corporation"},
+ {"AuthenticAMD","Advanced Micro Devices"},
+ {"CyrixInstead","Cyrix/VIA"},
+ {"NexGenDriven","NexGen"},
+ {"CentaurHauls","IDT/Centaur/VIA"},
+ {"RiseRiseRise","Rise"},
+ {"GenuineTMx86","Transmeta"}
+};
+
Modified: vic/branches/mpeg4/main.cpp
==============================================================================
--- vic/branches/mpeg4/main.cpp (original)
+++ vic/branches/mpeg4/main.cpp Thu Nov 16 10:26:25 2006
@@ -31,8 +31,7 @@
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
-static const char rcsid[] =
-"@(#) $Header$ (LBL)";
+
#include <stdio.h>
#include <stdlib.h>
@@ -70,7 +69,6 @@
#include <X11/Xutil.h>
extern "C" {
-#include "linux/cpudetect.h"
#include <tk.h>
#ifdef USE_SHM
#ifdef sgi
@@ -431,8 +429,8 @@
}
- int
-main(int argc, const char** argv)
+
+int main(int argc, const char** argv)
{
#ifdef __FreeBSD__
srandomdev(); //SV-XXX: FreeBSD
@@ -481,15 +479,7 @@
usage(NULL);
}
-#ifdef RUNTIME_CPUDETECT
- /* CPU capabilities detection */
- GetCpuCaps(&gCpuCaps);
- printf("cpudetect: %s\n", gCpuCaps.cpuname);
- printf("cpudetect: MMX=%d MMX2=%d SSE=%d SSE2=%d 3DNow=%d 3DNowExt=%d\n", \
- gCpuCaps.hasMMX, gCpuCaps.hasMMX2, gCpuCaps.hasSSE, gCpuCaps.hasSSE2, \
- gCpuCaps.has3DNow, gCpuCaps.has3DNowExt );
-#endif
-
+
Tcl::init("vic");
Tcl& tcl = Tcl::instance();
Modified: vic/branches/mpeg4/render/color-swscale.cpp
==============================================================================
--- vic/branches/mpeg4/render/color-swscale.cpp (original)
+++ vic/branches/mpeg4/render/color-swscale.cpp Thu Nov 16 10:26:25 2006
@@ -8,12 +8,14 @@
#include "config_arch.h"
#ifdef WIN32
#undef ARCH_X86
-// #include "ffmpeg_config.h"
#endif
#include "ffmpeg/swscale.h"
#include "ffmpeg/avutil.h"
-#include "linux/cpudetect.h"
+extern "C"{
+#include "cpu/cpudetect.h"
+}
+int available_cpu_flags = cpu_check();
#ifdef HAVE_SWSCALE
@@ -68,11 +70,11 @@
}
int flags = SWS_FAST_BILINEAR;
-#ifdef RUNTIME_CPUDETECT
- flags |= (gCpuCaps.hasMMX ? SWS_CPU_CAPS_MMX : 0);
- flags |= (gCpuCaps.hasMMX2 ? SWS_CPU_CAPS_MMX2 : 0);
- flags |= (gCpuCaps.has3DNow ? SWS_CPU_CAPS_3DNOW : 0);
- flags |= (gCpuCaps.hasAltiVec ? SWS_CPU_CAPS_ALTIVEC : 0);
+#ifdef RUNTIME_CPUDETECT
+ flags |= (available_cpu_flags & FF_CPU_MMX ? SWS_CPU_CAPS_MMX : 0);
+ flags |= (available_cpu_flags & FF_CPU_MMXEXT ? SWS_CPU_CAPS_MMX2 : 0);
+ flags |= (available_cpu_flags & FF_CPU_3DNOW ? SWS_CPU_CAPS_3DNOW : 0);
+ flags |= (available_cpu_flags & FF_CPU_ALTIVEC ? SWS_CPU_CAPS_ALTIVEC : 0);
#elif defined(HAVE_MMX)
flags |= SWS_CPU_CAPS_MMX;
#if defined(HAVE_MMX2)
Modified: vic/branches/mpeg4/vic.vcproj
==============================================================================
--- vic/branches/mpeg4/vic.vcproj (original)
+++ vic/branches/mpeg4/vic.vcproj Thu Nov 16 10:26:25 2006
@@ -14596,6 +14596,30 @@
RelativePath=".\postproc\config.h">
</File>
</Filter>
+ <Filter
+ Name="cpu"
+ Filter="">
+ <File
+ RelativePath=".\cpu\cpudetect.h">
+ </File>
+ <File
+ RelativePath=".\cpu\cpuid.asm">
+ <FileConfiguration
+ Name="Debug IPv6 XP|Win32">
+ <Tool
+ Name="VCCustomBuildTool"
+ Description="Assembling $(InputPath)"
+ CommandLine="nasmw -f win32 -DPREFIX -o "$(IntDir)\$(InputName).obj" $(InputPath)"
+ Outputs=""$(IntDir)\$(InputName).obj""/>
+ </FileConfiguration>
+ </File>
+ <File
+ RelativePath=".\cpu\cpuid.cpp">
+ </File>
+ <File
+ RelativePath=".\cpu\cputable.h">
+ </File>
+ </Filter>
<File
RelativePath="cm170.ppm">
<FileConfiguration
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